View ACPL-M72T-000E_6525010.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

acpl-m71t and acpl-m72t high speed, low power digital optocouplers with r 2 coupler? isolation and aec-q100 grade 1 qualifi cation data sheet caution: it is advised that normal static precautions be taken in handling and assembly of this component to prevent damage and/or degradation which may be induced by esd. features ? 5 v cmos compatible ? common-mode rejection 40kv/ ? s @ v cm =1000v: ? wide automotive temperature range: C40c to 125c ? low propagation delay : C high speed acpl-m71t: 26ns @ i f = 10 ma (typical) C low power acpl-m72t: 60ns @ i f = 4 ma (typical) ? worldwide safety approval: C ul 1577 recognized, 4000 vrms / 1 min C csa approved C iec/en/din en 60747-5-5 ? qualifi ed to aec-q100 grade 1 test guidelines applications ? automotive canbus communications interface ? automotive isolated high speed gate drivers for igbts and power mosfets ? high temperature digital signal isolation ? microcontroller interface ? digital isolation for a/d and d/a conversion description the avago acpl-m71t and acpl-m72t are high tem- perature, digital cmos optocouplers in soic-5 packages. suitable for hybrid and electric vehicle applications, the optocouplers use the latest cmos ic technology to achieve outstanding performance and very low power consumption. all devices are aec-q100 compliant and operate over the C40c to 125 c temperature range. the acpl-m71t uses a high speed led, and the acpl-m72t uses a low current led for lower power dissipation. the high speed acpl-m71t featuring a 35 ns maximum propagation delay (i f =10 ma). the acpl-m72t optocou- pler features very low power. with a low 4 ma led drive current, acpl-m72t typical propagation delay is 60 ns. each digital optocoupler has a cmos detector ic, an in- tegrated photodiode, a high speed transimpedance amplifi er, and a voltage comparator with an output driver. avago r 2 coupler isolation products provide the rein- forced insulation and reliability needed for critical in auto- motive and high temperature industrial applications functional block diagram note: a 0.1 ? f bypass capacitor must be connected between pins 4 and 6. 1 3 6 4 5 anode cathode vdd gnd v o acpl-m71t/acpl-m72t truth table led output (v o ) off h on l
2 ordering information part number option package surface mount tape & reel iec/en/din en 60747-5-2 quantity (rohs) compliant acpl-m71t -000e so-5 x 100 per tube -060e x x 100 per tube -500e x x 1500 per reel -560e x x x 1500 per reel acpl-m72t -000e so-5 x 100 per tube -060e x x 100 per tube -500e x x 1500 per reel -560e x x x 1500 per reel to order, choose a part number from the part number column and combine with the desired option from the option column to form an order entry. for example, the part number acpl-m71t-500e describes a device with a surface mount soic-5 package; delivered in tape and reel with 1500 parts per reel; and full rohs compliance. option datasheets are available. contact your avago sales representative or authorized distributor for information. package dimensions acpl-m71t / acpl-m72t (jedec mo-155 package) m71t yww ee 6 5 4 3 1 7.0 0.2 (0.276 0.008) 2.5 0.1 (0.098 0.004) 0.102 0.102 (0.004 0.004) v cc v out gnd cathode anode 4.4 0.1 (0.173 0.004) 1.27 (0.050) bsc 0.20 0.025 (0.008 0.001) 0.71 (0.028) min 0.4 0.05 (0.016 0.002) 3.6 0.1* (0.142 0.004) dimensions in millimeters (inches) * maximum mold flash on each side is 0.15 mm (0.006) note: floating lead protrusion is 0.15 mm (6 mils) max. extended datecode for lot tracking 7 max. max. lead coplanarity = 0.102 (0.004)
3 land pattern recommendation 8.27 (0.325) 2.0 (0.080) 2.5 (0.10) 1.3 (0.05) 0.64 (0.025) 4.4 (0.17) dimension in millimeters (inches) ul approved under ul 1577, component recognition program up to v iso = 4000 v rms expected prior to product release. csa approved under csa component acceptance notice #5. iec/en/din en 60747-5-2 iec 60747-5-5: en 60747-5-2: din en 60747-5-2: recommended pb-free ir profi le recommended refl ow condition as per jedec standard, j-std-020 (latest revision). note: non-halide fl ux should be used. regulatory information the acpl-m71t and acpl-m72t are approved by the following organizations:
4 insulation and safety related specifi cations parameter symbol value units conditions minimum external air gap (clearance) l(i01) >5 mm measured from input terminals to output terminals, shortest distance through air. minimum external tracking (creepage) l(i02) >5 mm measured from input terminals to output terminals, shortest distance path along body. minimum internal plastic gap (internal clearance) 0.08 mm insulation thickness between emitter and detector; also known as distance through insulation. tracking resistance (comparative tracking index) cti >175 volts din iec 112/vde 0303 part 1 isolation group iiia material group (din vde 0109) iec/en/din en 60747-5-2 insulation related characteristics description symbol acpl-m71t/ acpl-m72t units maximum working insulation voltage v iorm 567 v peak input to output test voltage, method b ? v iorm x 1.875 = v pr , 100% production test with t m = 1 sec, partial discharge < 5 pc v pr 1067 v peak input to output test voltage, method a ? v iorm x 1.6 = v pr , type and sample test, t m = 10 sec, partial discharge < 5 pc v pr 907 v peak highest allowable overvoltage ? (transient overvoltage, t ini = 60 sec) v iotm 6000 v peak safety limiting values (maximum values allowed in the event of a failure, also see thermal derating curve, figure 11.) case temperature t s 150 c input current i s, input 150 ma output power p s,output 600 mw insulation resistance at t s , v io = 500 v r io 10 9 ?
5 absolute maximum ratings parameter symbol min. max. units condition storage temperature t s C55 +130 c ambient operating temperature [1] t a C40 +125 c supply voltages v dd 0 6.5 volts output voltage v o C0.5 v dd +0.5 volts average forward input current i f C 20.0 ma peak transient input current (i f at 1us pulse width, <10% duty cycle) i f( tran) 1 80 a ma <1us pulse width, 300pps <1us pulse width, <10%duty cycle reverse input voltage v r C5v input power dissipation p i 40 mw output power dissipation p o 30 mw lead solder temperature 260c for 10 sec., 1.6 mm below seating plane solder refl ow temperature profi le see solder refl ow temperature profi le section recommended operating conditions parameter symbol min. max. units ambient operating temperature t a C40 +125 c supply voltages v dd 3.0 5.5 v forward input current i f(on) 4.0 15 ma forward off state voltage v f (off) 0.8 v input threshold current i th 3.5 ma
6 electrical specifi cations over recommended temperature (t a = C40c to +125c), 3.0 v v dd 5.5 v. all typical specifi cations are at t a =+25c, v dd = +5v. parameter symbol min. typ. max. units test conditions fig input capacitance c in 90 pf input reverse breakdown voltage bv r 5.0 v i r = 10 ? a logic high output voltage v oh v dd -0.6 v i oh = -4ma 4 logic low output voltage v ol 0.6 v i ol = 4ma 3 logic low output supply current i ddl 0.9 1.5 ma logic high output supply current i ddh 0.9 1.5 ma led forward voltage vf 1.45 1.5 1.75 v i f =10ma, ta=25c 1.25 1.5 1.85 v i f =10ma, ta= -40c ~ 125c vf temperature coefi cient -1.5 mv/c acpl-m71t high speed mode switching specifi cations over recommended temperature (t a = C40c to +125c), 4.5 v v dd 5.5 v. all typical specifi cations are at t a =+25c, v dd = 5v. parameter symbol min. typ. max. units test conditions fig note propagation delay time to logic low output [1] t phl 26 35 ns v in =4.5v-5.5v, r in =390 ? +/-5%, c in =100pf, c l = 15pf 5,6,11 1,2,3 propagation delay time to logic high output [1] t plh 26 35 ns pulse width distortion [2] pwd 0 12 ns propagation delay skew [3] t psk 15 ns output rise time (10% C 90%) t r 10 ns output fall time (90% - 10%) t f 10 ns common mode transient immunity at logic high output [4] | cm h |15 25 kv/ ? sv in =0v rin=390 ? +/-5%, c in =100pf, v cm =1000v, t a =25c 12 4 common mode transient immunity at logic high output [5] | cm l |15 25 kv/ ? s v in =4.5v-5.5v , r in =390 ? +/-5%, c in =100pf, v cm =1000v, t a =25c 13 5
7 acpl-m72t low power mode switching specifi cations over recommended temperature (-40c to +125c), 3.0v v dd 5.5v. all typical specifi cations at +25c and vdd = 5v parameter symbol min. typ. max. units test conditions fig note propagation delay time to logic low output [1] t phl 60 100 ns i f =4ma, c l =15pf 7,8, 9,10, 14 1,2,3 propagation delay time to logic high output [1] t plh 35 100 ns pulse width distortion [2] pwd 25 50 ns propagation delay skew [3] t psk 60 ns output rise time (10% C 90%) t r 10 ns output fall time (90% - 10%) t f 10 ns common mode transient immunity at logic high output [4] | cm h |25 40 kv/ ? s using avago led driving circuit, v in =0v, r 1 =350 ? +/-5% , r 2 =350 ? +/-5%, v cm =1000v, t a =25c 15 4 common mode transient immunity at logic high output [5] | cm l |25 40 kv/ ? s using avago led driving circuit, v in =4.5-5.5v, r 1 =350 ? +/-5% , r 2 =350 ? , v cm =1000v, t a =25c 16 5 package characteristics all typical at t a = 25c. parameter symbol min. typ. max. units test conditions input-output momentary withstand voltage v iso 4000 v rms rh 50%, t = 1 min., t a = 25c input-output resistance r i-o 10 14 ? v i-o = 500 v dc input-output capacitance c i-o 0.6 pf f = 1 mhz, t a = 25c notes: 1. t phl propagation delay is measured from the 50% (vin or if ) on the rising edge of the input pulse to 0.8v on the falling edge of th e v o signal. t plh propagation delay is measured from the 50% (vin or if ) on the falling edge of the input pulse to the 80% level of the rising ed ge of the v o signal. 2. pwd is defi ned as |t phl - t plh |. 3. t psk is equal to the magnitude of the worst case diff erence in t phl and/or t plh that will be seen between units at any given temperature within the recommended operating conditions. 4. cm h is the maximum tolerable rate of rise of the common mode voltage to assure that the output will remain in a high logic state. 5. cm l is the maximum tolerable rate of fall of the common mode voltage to assure that the output will remain in a low logic state.
8 0.0 1 0. 1 0 1 .00 1 0.00 1 00.00 1 .2 1 .3 1 .4 1 .5 1 .6 v f - f or w ard v o lt age - v i f - f or w ard c u rre nt - ma i f - f or w ard c u rre nt ( ma ) t a = 25c 0 1 2 3 4 5 00.5 11 .5 2 v o - o utput v o lt age (v) 4.0 4.2 4.4 4.6 4.8 5.0 -1 0 - 8 - 6 - 4 - 2 0 i o h - l ogic h ig h o utput c u rre nt - ma v o h - l ogic h ig h o utput v o lt age - v 0.000 0. 1 00 0.200 0.300 0.400 0.500 0.600 0.700 02468 1 0 i o l - l ogic l o w o utput c u rre nt - ma v o l - l ogic l o w o utput v o lt age - v 0 5 1 0 1 5 20 25 30 35 40 - 40 - 200 20406080 1 00 1 20 1 40 t em p era tu re - c tp - pro p aga t io n de l a y, p w d - p ul se w id th dis t or t io n - n s t p hl v i n= 4.5 v, ri n= 390 : , ci n=1 00 pf t p lh p w d - 5 0 5 1 0 1 5 20 25 30 35 40 3456789 1 0 11 1 2 1 3 1 4 1 5 i f - f or w ard c u rre nt - ma tp - pro p aga t io n de l a y, p w d - p ul se w id th dis t or t io n - n s t p hl ri n= 390 : , ci n=1 00 pf t p lh t a = 25c p w d figure 5. acpl-m71t (high speed)typical propagation delay vs temperature figure 4. typical logic high output voltage vs logic high output current figure 3. typical logic low output voltage vs logic low output current figure 2. typical output voltage vs input forward current figure 1. typical diode input forward current characteristic performance plots figure 6. acpl-m71t (high speed)typical propagation delay vs forward current - i f
9 figure 8. acpl-m72t (5v) typical propagation delay vs forward current - i f figure 7. acpl-m72t (5v) typical propagation delay vs temperature - 5 0 5 1 0 1 5 20 25 30 35 40 45 50 - 40 - 200 20406080 1 00 1 20 t em p era tu re - c w id th dis t or t io n - n s -1 0 - 5 0 5 1 0 1 5 20 25 30 35 40 45 50 55 60 3456789 1 0 11 1 2 1 3 1 4 1 5 i f - f or w ard c u rre nt - ma tp - pro p aga t io n de l a y, p w d - p ul se w id th dis t or t io n - n s t p hl i f = 4ma t p lh p w d t p hl t p lh t a = 25c p w d t a - t em p era tu re - c i f - f or w ard c u rre nt - ma 0 1 0 20 30 40 50 60 70 80 90 - 40 - 20 0 20406080 1 00 1 20 t p - pro p aga t io n de l a y - n s i f = 4ma , v dd = 3 v t p hl t p lh p w d 0 1 0 20 30 40 50 60 70 80 3456789 1 0 11 1 2 1 3 1 4 1 5 t p - pro p aga t io n de l a y - n s t p hl t p lh p w d t a = 25 c , v dd = 3 v figure 10. acpl-m72t (3v) typical propagation delay vs input forward current figure 9. acpl-m72t (3v) typical propagation delay vs temperature
10 figure 12. high speed mode cmh test circuit and typical waveform figure 11. high speed mode test circuit and typical waveform test circuit diagrams acpl-m71t high speed mode: 0. 1 f b yp ass ca p ou t pu t v o mon it or i ng nod e s hiel d 1 3 6 4 5 r 1= 390 5 % v dd = 5 v c l =1 5 pf acp l- m7 1t v i n= 4.5 - 5.5 v ci n=1 00 pf gnd2 gnd 1 gnd2 0. 1 f b yp ass ca p ou t pu t v o mon it or i ng nod e s hiel d + ? 1 3 6 4 5 r 1= 390 5 % v dd = 5 v h ig h v o lt age p ul se v cm = 1 000 v c l =1 5 pf acp l- m7 1t v i n= 4.5 - 5.5 v ci n=1 00 pf 0 v o t phl t plh 80 % v dd v dd v ol v in 2 v in 2 0.8 v v in v dd-1 5 v 0 v switch at a: i f = 0 ma v cm cm h v cm (peak) v o gnd2 figure 13. high speed mode cml test circuit and typical waveform gnd2 0. 1 f b yp ass ca p ou t pu t v o mon it or i ng nod e s hiel d + ? 1 3 6 4 5 r 1= 390 5 % v dd = 5 v h ig h v o lt age p ul se v cm = 1 000 v c l =1 5 pf acp l- m7 1t v i n= 4.5 - 5.5 v ci n=1 00 pf v o gnd2 0 v s wit c h a t a: i f = 0 ma v cm cm l 1v v cm ( p e a k)
11 figure 15. low power mode high cmr, cmh test circuit figure 16. low power mode high cmr, cml test circuit gnd2 0. 1 f b yp ass ca p ou t pu t v o mon it or i ng nod e s hiel d + ? 1 3 6 4 5 r 1= 350 v dd = 5 v r2 = 350 h ig h v o lt age p ul se v cm = 1 000 v c l =1 5 pf acp l- m72 t gnd2 0. 1 f b yp ass ca p ou t pu t v o mon it or i ng nod e s hiel d + ? 1 3 6 4 5 r 1= 350 v dd = 5 v r2 = 350 h ig h v o lt age p ul se v cm = 1 000 v c l =1 5 pf acp l- m72 t v i n = 4.5 - 5.5 v acpl-m72t low power mode: figure 14. low power mode switching test circuit and typical waveform gnd2 0.1 f b yp ass ca p output vo monitoring node shield 1 3 6 4 5 rin=700 vdd=5 v c l =15 p f acpl-m72t gnd1 input monitoring node pulse gen. 0 v o t phl t plh 80 % v dd v dd v ol v in 2 v in 2 0.8 v v in
for product information and a complete list of distributors, please go to our web site: www.avagotech.com avago, avago technologies, the a logo and r 2 coupler? are trademarks of avago technologies in the united states and other countries. data subject to change. copyright ? 2005-2012 avago technologies. all rights reserved. av02-2180en - february 10, 2012 application circuits figure 17. recommended application circuit for acpl-m71t high speed performance figure 18. recommended application circuit for acpl-m72t low power performance truth table vin led vout lonl h off h truth table vin led vout lonl h off h logic i/o cin vdd ro gnd2 0.1 f b yp ass ca p vout gnd1 vin shield r limit logic i/o vdd ro gnd2 0.1 f b yp ass ca p vout gnd1 vin shield ?r limit ?r limit

▲Up To Search▲

Price & Availability of ACPL-M72T-000E

	To Download ACPL-M72T-000E Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .